Semiconductor structure and methods for bonding tested wafers and testing pre-bonded wafers
US12176320B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 23, 2022 |
| Grant date | Dec 24, 2024 |
| Priority date | — |
| Expiry date | May 31, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1436
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for bonding tested wafers is provided. The method includes the following operations. A first wafer having a first surface is received, and the first wafer includes a test pad and a conductive pad at the first surface of the first wafer and the test pad has a recess caused by a test probe and the conductive pad is electrically connected to the test pad. The first surface of the first wafer is planarized. A first hybrid bonding layer is formed over the first surface of the first wafer. The first wafer and a second wafer are bonded to connect the first hybrid bonding layer and a second hybrid bonding layer on the second water. A semiconductor structure and a method for testing pre-bonded wafers are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.