Radio frequency switch biasing topologies
US12176893B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 21, 2023 |
| Grant date | Dec 24, 2024 |
| Priority date | — |
| Expiry date | Aug 21, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/1615
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A switching circuit comprises a first series switch coupled to a first output port, the first series switch including a first field-effect transistor (FET), a second FET, a third FET, a fourth FET, a fifth FET, and a sixth FET, a second series switch coupled to a second output port, and coupling circuitry configured to couple a gate of the fifth FET and a gate of the sixth FET to a first node, a source of the fifth FET and a drain of the sixth FET to a second node, a source of the first FET and a drain of the second FET to a third node, a gate of the first FET and a drain of the fifth FET to a fourth node, a gate of the second FET and a source of the sixth FET to a fifth node, the fourth node and the fifth node to a first gate voltage, and the first node to a second gate voltage that is different than the first gate voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.