Systems for and methods of jitter reduction
US12176907B2 · kind B2 · utility
0Cited by
4References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 27, 2022 |
| Grant date | Dec 24, 2024 |
| Priority date | — |
| Expiry date | Dec 27, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system for controlling jitter includes a first phase interpolator, a second phase interpolator, a first circuit configured to receive a first signal provided to the first phase interpolator, a second circuit configured to receive a second signal provided to the second phase interpolator, and a third circuit configured to provide a phase control signal in response to the first signal and the second signal. The first signal represents a first phase adjustment, and the second signal represents a second phase adjustment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.