Error correction code circuit, memory device including error correction code circuit, and operation method of error correction code circuit
US12176919B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2022 |
| Grant date | Dec 24, 2024 |
| Priority date | — |
| Expiry date | Jan 4, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/616
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed is a memory device which includes a memory cell array that stores first data and first parity data, an error correction code (ECC) circuit that performs ECC decoding based on the first data and the first parity data and outputs error-corrected data and a decoding status flag, and an input/output circuit that provides the error-corrected data and the decoding status flag to a memory controller. The ECC circuit includes a syndrome generator that generates a syndrome based on the first data and the first parity data, a syndrome decoding circuit that decodes the syndrome to generate an error vector, a correction logic circuit that generates the error-corrected data based on the error vector and the first data, and a fast decoding status flag (DSF) generator that generates the decoding status flag based on the syndrome, without the error vector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.