Hardware-assisted digital fault relay for sub-50ms optical protection
US12177114B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 5, 2023 |
| Grant date | Dec 24, 2024 |
| Priority date | — |
| Expiry date | Sep 5, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q11/0062
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Optical networks and nodes are described herein, including an optical network comprising a head-end node and a tail-end node. A line module of the head-end node receives fault information, generates a fault packet, and sends the fault packet to a first node controller identified by first packet forwarding information included in a packet header of the fault packet. The first node controller retrieves second packet forwarding information using the first packet forwarding information, updates the packet header, and sends the fault packet to the tail-end node identified by the second packet forwarding information. A second node controller of the tail-end node retrieves third packet forwarding information using the second packet forwarding information, updates the packet header, and sends the fault packet to an optical protection switching module (OPSM) of the tail-end node identified by the second packet forwarding information. The OPSM switches an optical switch based on the fault information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.