Power supply rejection enhancer
US12181903B2 · kind B2 · utility
0Cited by
25References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 10, 2023 |
| Grant date | Dec 31, 2024 |
| Priority date | — |
| Expiry date | May 10, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/16
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
In certain aspects, a system includes an amplifying circuit having an input and an output, a high-pass filter coupled between a gate of a pass transistor of a low dropout (LDO) regulator and the input of the amplifying circuit, and a metal-oxide-semiconductor (MOS) capacitor coupled between the output of the amplifying circuit and the gate of the pass transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.