Automatic overclocking controller based on circuit delay measurement
US12181911B2 · kind B2 · utility
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5Claims
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Key dates
| Filing date | Jul 21, 2023 |
| Grant date | Dec 31, 2024 |
| Priority date | — |
| Expiry date | Aug 23, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B17/364
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An automatic overclocking controller based on circuit delay measurement is provided, including a central processing unit (CPU), a clock generator, and a timing delay monitor (TDM) controller. Compared with the prior art, the present disclosure has following innovative points: A two-dimension-multi-frame fusion (2D-MFF) technology is used to process a sampling result, to eliminate sampling noise, and an automatic overclocking controller running on a heterogeneous field programmable gate array (FPGA) can automatically search for a highest frequency at which an accelerator can operate safely.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.