Patent · US Active

Clock synchronization pulse width scaling

US12181913B2 · kind B2 · utility

0Cited by

2References

18Claims

0Family size

Assignee

TEXAS INSTRUMENTS INCORPORATED · US

Inventors

Atul Ramakant Lele · Kanchinakote, IN
Paul J. Patchen · Homewood, US
Ryan Smith · Sachse, US
Bernd Hannes Schneider · Freising, DE

Key dates

Filing date	Dec 27, 2021
Grant date	Dec 31, 2024
Priority date	—
Expiry date	Dec 27, 2041

Classification

Technology area (CPC H)Electricity
CPC primaryH03K21/023
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An electronic circuit includes an oscillator circuit, a first divider circuit, a synchronization control circuit, and a peripheral circuit. The oscillator circuit is configured to generate a base frequency clock. The first divider circuit is configured to divide the base frequency clock by a first selectable divisor to generate a divided clock. The synchronization control circuit is configured to generate a synchronization pulse that controls a change of the first selectable divisor in the first divider circuit from a first value to a second value. A pulse width of the synchronization pulse is based on the first value of the first selectable divisor. The peripheral circuit is coupled to the first divider circuit and the synchronization control circuit. The peripheral circuit includes a second divider circuit. The second divider circuit divides the divided clock by a second selectable divisor, and change the second selectable divisor responsive to the synchronization pulse.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.