Patent · US Active

Providing content-aware cache replacement and insertion policies in processor-based devices

US12182036B2 · kind B2 · utility

0Cited by

1References

14Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

George Patsilaras · San Diego, US
Engin Ipek · Pittsford, US
Goran Goran · San Diego, US
Hamza Omar · San Diego, US
Bohuslav Rychlik · San Diego, US
Jeffrey Gemar · San Diego, US
Matthew Severson · Austin, US
Andrew E. Turner · San Diego, US

Key dates

Filing date	Feb 2, 2023
Grant date	Dec 31, 2024
Priority date	—
Expiry date	Feb 2, 2043

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/502
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Providing content-aware cache replacement and insertion policies in processor-based devices is disclosed. In some aspects, a processor-based device comprises a cache memory device and a cache controller circuit of the cache memory device. The cache controller circuit is configured to determine a plurality of content costs for each of a plurality of cached data values in the cache memory device, based on a plurality of bit values of each of the plurality of cached data values. The cache controller circuit is configured to identify, based on the plurality of content costs, a cached data value of the plurality of cached data values associated with a lowest content cost as a target cached data value. The cache controller circuit is also configured to evict the target cached data value from the cache memory device.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.