Communication system based on parallel bus
US12182054B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2021 |
| Grant date | Dec 31, 2024 |
| Priority date | — |
| Expiry date | Dec 15, 2041 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a parallel bus-based communication system, the system including: electronic devices; a host controller equipped with a selecting chip and a communication chip, and the communication chip controls at least one channelized parallel bus, and the electronic devices are individually connected to the channelized parallel bus. The host controller, upon first power on, allocates addresses to the electronic device sequentially via the selecting chip. In the present disclosure, the communication chip of the communication system employs a parallel bus communication mode, and the selecting chip sequentially allocates addresses to the electronic device. Communication functions can be achieved by using a small number of communication chips. The electronic devices (sensors) are independent of each other and do not affect one another. The existing sensor structures and vehicle harness may be used, which has cost advantages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.