Power control logic using inter-chip
US12182055B1 · kind B1 · utility
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20Claims
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Key dates
| Filing date | Dec 13, 2022 |
| Grant date | Dec 31, 2024 |
| Priority date | — |
| Expiry date | Dec 13, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0038
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and techniques for power delivery to an electronic device using multiple power management integrated circuits (PMICs) are described herein. The systems and techniques provide for two signal connections between each of the PMICs to sync transition signals on a first line and provide faults to interrupt operations on a second line. The PMICs are connected to an electronic device that commands power transitions for voltage rails from the PMICs with the commands received over I2C communication from the electronic device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.