System architecture to selectably synchronize time-bases
US12182060B2 · kind B2 · utility
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Key dates
| Filing date | Mar 27, 2023 |
| Grant date | Dec 31, 2024 |
| Priority date | — |
| Expiry date | Apr 12, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system timer bus used by the processor elements in an ARM-based system on a chip (SoC) is driven using a Precision Time Measurement (PTM) value. This allows the processor elements to be synchronized to the PCIe ports that use PTM. When two SoCs are connected using PCIe links, this example allows the processor elements in both SoCs to be synchronized. As the processor elements are synchronized, associated tasks on the two SoCs are synchronized, so that overall operations are synchronized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.