System and method for detecting fault injection attacks
US12182260B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 30, 2021 |
| Grant date | Dec 31, 2024 |
| Priority date | — |
| Expiry date | Dec 2, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/2113
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A security system configured for deployment on a chip which is to be protected, the system comprising fault injection detection subsystem/s configured for deployment on the chip, each fault injection detection subsystem having plural sensitivity levels which are selectable in real time and comprising at least one hardware fault injection detector circuit/s, configured for deployment on the chip, and/or, coupled thereto, sensitivity level control logic which may be configured for deployment on the chip and which may be operative, in real time, to transition the fault injection detection subsystem, from its current sensitivity level from among said plural selectable sensitivity levels, to a next sensitivity level from among said plural selectable sensitivity levels, e.g. by generating sensitivity control signals (aka sensitivity level selections) and/or feeding the sensitivity control signals to at least one hardware fault injection detector in the subsystem.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.