Signal processing in bridge chip in semiconductor storage device and memory system
US12182411B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 28, 2023 |
| Grant date | Dec 31, 2024 |
| Priority date | — |
| Expiry date | Mar 5, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor storage device includes a plurality of semiconductor memory chips and a bridge chip. The bridge chip includes a first interface connectable to an external memory controller that is external to the semiconductor storage device, a plurality of second interfaces connected to the semiconductor memory chips, and a controller. The controller is configured to, upon receiving, by the first interface, a first command sequence that includes a data transfer command to perform data transfer with one of the semiconductor chips and size information indicating a size of data to be transferred, start an operation to perform the data transfer, and end the operation, upon an amount of data that has been received by the first interface during the data transfer reaching the size indicated by the size information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.