High clock-efficiency random number generation system and method
US12182535B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 1, 2023 |
| Grant date | Dec 31, 2024 |
| Priority date | — |
| Expiry date | Feb 1, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30134
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for aggregating data and for generating a stream of random numbers. There is a data bus, having a bus input with first and second output switching inputs that each mask values input thereto such that data from both the first and second output switching inputs are aggregated into the bus according to the masking thereof, and a bus output. There is also a data loop of random numbers having a data loop output port functionally coupled to the bus input through the first output switching input; a data feed having an output functionally coupled to the bus input through the second output switching input; and an active data operator coupled to the bus output such that data aggregated by the bus from the data loop and the first data feed is fed to the data operator, the output thereof being a stream of random numbers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.