Processing device with vector transformation execution
US12182573B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Sep 20, 2023 |
| Grant date | Dec 31, 2024 |
| Priority date | — |
| Expiry date | Sep 20, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3887
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit, comprising an instruction pipeline that includes instruction fetch phase circuitry, instruction decode phase circuitry, and instruction execution circuitry. The instruction execution circuitry includes transformation circuitry for receiving an interleaved dual vector operand as an input and for outputting a first natural order vector including a first set of data values from the interleaved dual vector operand and a second natural order vector including a second set of data values from the interleaved dual vector operand.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.