Operation method of memory device, and operation method of memory controller controlling memory device
US12183402B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 2022 |
| Grant date | Dec 31, 2024 |
| Priority date | — |
| Expiry date | Mar 30, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/349
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is an operation method of a memory device that includes a memory block including a plurality of cell transistors stacked in a direction perpendicular to a substrate. The plurality of cell transistors may include a ground selection transistor and an erase control transistor. The erase control transistor may be between the substrate and the ground selection transistor. The operation method may include performing a first erase operation on the ground selection transistor, performing a first program operation on the erase control transistor after the first erase operation, performing a second program operation on the ground selection transistor after the first program operation, and performing a second erase operation on the erase control transistor after the second program operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.