Memory interface circuitry and built-in self-testing method
US12183411B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2023 |
| Grant date | Dec 31, 2024 |
| Priority date | — |
| Expiry date | Aug 26, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory interface circuitry includes a clock generator to convert the first clock signal into a second clock signal, a state machine to generate a test signal according to the second clock signal, a data pattern generator to generate a plurality of pre-defined data, a read register to sequentially output the plurality of pre-defined data, an I/O interface to capture a plurality of data from the plurality of pre-defined data according to a write strobe signal, a write register to receive and store the plurality of data from the I/O interface, and a comparator to compare the plurality of pre-defined data with the plurality of data to generate a test result. The test result is configured to verify an operation of the I/O interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.