Input buffer circuit and semiconductor memory
US12183423B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 27, 2022 |
| Grant date | Dec 31, 2024 |
| Priority date | — |
| Expiry date | Apr 4, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018507
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments provide an input buffer circuit and a semiconductor memory, a compensation subcircuit is provided between an input terminal of the input buffer circuit and a first terminal of a load subcircuit, a current of an output terminal of the input buffer circuit is increased, and voltage variation of the input terminal can be transmitted to the output terminal in time, such that the output terminal can timely receive the voltage variation of the input terminal, thereby avoiding distortion of an output signal, solving a problem of signal attenuation for the input buffer circuit, improving sensitivity of the input buffer circuit, and preventing negative effects from being caused to transmission of commands inside a system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.