Data reading/writing method, memory, storage apparatus, and terminal
US12183425B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 22, 2022 |
| Grant date | Dec 31, 2024 |
| Priority date | — |
| Expiry date | Jan 24, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory includes S storage blocks, N global bitlines, and a signal amplification circuit. Each of the S storage blocks is connected to the N global bitlines, the N global bitlines are connected to the signal amplification circuit, the signal amplification circuit is configured to amplify electrical signals on the N global bitlines, and each storage block includes N columns of storage units, N local bitlines, and N bitline switches. In each storage block, storage units in an ith column are connected to an ith local bitline, the ith local bitline is connected to an ith global bitline by using an ith bitline switch in the N bitline switches. A memory array is fine-grained, so that ith local bitlines in the S storage blocks can share one global bitline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.