Semiconductor structure and chip
US12183431B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 9, 2023 |
| Grant date | Dec 31, 2024 |
| Priority date | — |
| Expiry date | Jun 28, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure and a chip are provided. The semiconductor structure includes: a first active area and a second active area extending along a first direction and having a first width in a second direction; a first WordLine (WL) drive transistor group including two gate dielectric areas connected to the first active area; a second WL drive transistor group including two gate dielectric areas connected to the first active area; a third WL drive transistor group including two gate dielectric areas connected to the second active area; and a fourth WL drive transistor group including two gate dielectric areas connected to the second active area. Each of the gate dielectric area extends along the second direction and has a second width in the first direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.