Chip structure with etch stop layer
US12183674B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2023 |
| Grant date | Dec 31, 2024 |
| Priority date | — |
| Expiry date | Jun 20, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L24/05
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip structure is provided. The chip structure includes a substrate. The chip structure includes an interconnect structure over the substrate. The chip structure includes a conductive pad over the interconnect structure. The chip structure includes a passivation layer covering the interconnect structure and exposing the conductive pad. The chip structure includes a first etch stop layer over the passivation layer. The chip structure includes a first buffer layer over the first etch stop layer. The first etch stop layer and the first buffer layer are made of different materials. The chip structure includes a second etch stop layer over the first buffer layer. The second etch stop layer and the first buffer layer are made of different materials. The chip structure includes a device element over the second etch stop layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.