Array substrate
US12183752B2 · kind B2 · utility
1Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 24, 2021 |
| Grant date | Dec 31, 2024 |
| Priority date | — |
| Expiry date | May 24, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/8057
Abstract
An array substrate is disclosed. The array substrate includes a semiconductor layer integrated with a PIN photoelectric diode and an active area. The PIN photoelectric diode includes a P-type semiconductor area, an N-type semiconductor area, and an I-type semiconductor area defined between the P-type semiconductor area and the N-type semiconductor area. A gate electric current is introduced at a location corresponding to the I-type semiconductor area, so as to enhance light sensitivity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.