Method for forming capacitor via
US12183776B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2021 |
| Grant date | Dec 31, 2024 |
| Priority date | — |
| Expiry date | Dec 28, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a capacitor via includes: providing a to-be-processed wafer, the to-be-processed wafer including a substrate and a first dielectric layer and a first mask layer that are sequentially formed on a surface of the substrate; etching the first mask layer according to a compensated first etching parameter, to form a first patterned layer extending in a first etching direction; sequentially forming a second dielectric layer and a second mask layer on a surface of the first patterned layer; etching the second mask layer and the second dielectric layer according to a compensated second etching parameter, to form a second patterned layer extending in a second etching direction; and etching the first dielectric layer with the first patterned layer and the second patterned layer together as a capacitor pattern, to form a capacitor via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.