Power semiconductor device and manufacturing method therefor
US12183818B2 · kind B2 · utility
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4References
20Claims
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Key dates
| Filing date | Dec 23, 2019 |
| Grant date | Dec 31, 2024 |
| Priority date | — |
| Expiry date | May 3, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/64
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A power semiconductor device includes: a substrate; drain metal; a drift region; a base region; a gate structure; a first conductive type doped region contacting the base region on the side of the base region distant from the gate structure; a source region provided in the base region and between the first conductive type doped region and the gate structure; contact metal that is provided on the first conductive type doped region and forms a contact barrier having rectifying characteristics together with the first conductive type doped region below; and source metal wrapping the contact metal and contacting the source region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.