Patent · US Active

Fault detection within an analog-to-digital converter

US12184297B2 · kind B2 · utility

0Cited by

8References

21Claims

0Family size

Assignee

TEXAS INSTRUMENTS INCORPORATED · US

Inventors

Veeramanikandan Raju · Bengaluru, IN
Anand Kumar G · Bengaluru, IN

Key dates

Filing date	Jan 25, 2023
Grant date	Dec 31, 2024
Priority date	—
Expiry date	Apr 6, 2043

Classification

Technology area (CPC H)Electricity
CPC primaryH03M1/122
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A circuit includes an analog-to-digital converter (ADC) having selectable first and second analog channel inputs; a window comparator that compares a digital value output by the ADC to first and second threshold values defining a window and that asserts a trigger signal in response to the digital value being outside the window; a programmable clock circuit that provides a clock signal to the ADC; a controller that generates, in response to assertion of the trigger signal, a sample rate control signal to cause the clock circuit to increase the frequency of the clock signal and toggle selection between the first and second analog channel inputs; and comparison circuitry that compares a first digital output from the ADC to a second digital output from the ADC.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.