Configuration of ADC data rates across multiple physical channels
US12184299B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2022 |
| Grant date | Dec 31, 2024 |
| Priority date | — |
| Expiry date | Mar 8, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/303
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a set of N unit analog-to-digital converters (ADCs) having a common architecture, and which provide an aggregate data rate. Moreover, the integrated circuit includes control logic that selects subsets of the set of N unit ADCs in order to realize sub-ADCs of different data rates that can each be an arbitrary integer multiple of an inverse of N times the aggregate data rate of the N unit ADCs. Furthermore, the control logic may dynamically select the subsets on the fly or on a frame-by-frame basis. This dynamically selection may occur at boot time and/or a runtime. Additionally, the given different data rate may correspond to one or more phases of a multi-phase clock in the integrated circuit, where the multiphase clock may include a number of phases corresponding to a number of possible subsets, and given selected subsets may not use all of the available phases.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.