Low power mmWave receiver architecture with spatial compression interface
US12184316B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2022 |
| Grant date | Dec 31, 2024 |
| Priority date | — |
| Expiry date | Aug 23, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/70
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A receiver circuit associated with a communication device is disclosed. The receiver circuit comprises a digital data compression circuit configured to receive a plurality of digital receive signals derived from a plurality of analog receive signals respectively associated with the receiver circuit. The digital data compression circuit is further configured to compress the plurality of digital receive signals to form one or more compressed digital data signals based thereon, to be provided to an input output (I/O) interface associated therewith. In some embodiments, a compressed digital signal dimension associated with the one or more compressed digital data signals is less than a digital signal dimension associated with the plurality of digital receive signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.