Reconciling events in multi-node systems using hardware timestamps
US12184404B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 5, 2021 |
| Grant date | Dec 31, 2024 |
| Priority date | — |
| Expiry date | Dec 30, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0038
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are described for reconciling events timestamped in different time domains in multi-node systems supporting low-latency hardware timestamping. First and second nodes having independent time bases are synchronized by the first node generating an event that is received effectively simultaneously at the first and second nodes, the first and second nodes recording a timestamp of receipt of the event, the first node asynchronously querying the second node for its timestamp of receipt of the event and comparing its timestamp of receipt of the event with the timestamp of receipt of the event by the second node, and the first node using a difference in the timestamps of receipt of the event by the first and second nodes to align the time bases of the first and second nodes. The nodes may include hardware timestamping functionality or use an external component (e.g., field programmable gate array) to provide the timestamping functionality.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.