Method for manufacturing memory device and memory
US12185521B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 6, 2021 |
| Grant date | Dec 31, 2024 |
| Priority date | — |
| Expiry date | Aug 6, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4091
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the disclosure provide a method for manufacturing a memory device, the method includes operations. At least one cell block is formed on a wafer, each of the at least one cell block includes multiple memory cells distributed in an array, each of the multiple memory cells includes a transistor and a storage capacitor connected to a source of the transistor. Bit lines are formed on the wafer, and each of the bit lines is connected to a drain of the transistor, here each of the bit lines and the storage capacitor are located on opposite surfaces of the wafer in a thickness direction respectively. A peripheral circuit is formed above the bit lines on the wafer along a perpendicular of the wafer, here the peripheral circuit includes at least a Sensing Amplifier (SA). An electrical connection is formed between the bit line and the SA.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.