Method for manufacturing semiconductor substrate, method for manufacturing damascene wiring structure, semiconductor substrate, and damascene wiring structure
US12187607B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2019 |
| Grant date | Jan 7, 2025 |
| Priority date | — |
| Expiry date | Aug 26, 2041 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB81C2201/0181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor substrate according to an embodiment includes a first step of forming a groove having a bottom surface and a side surface on which scallops are formed by performing a process including isotropic etching on a main surface of a substrate, a second step of performing at least one of a hydrophilic treatment on the side surface of the groove and a degassing treatment on the groove, and a third step of removing the scallops formed on the side surface of the groove and planarizing the side surface by performing anisotropic wet etching in a state where the bottom surface of the recess is present.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.