Circuit and method for post-binding testing of 2.5D chiplet

US12188984B1 · kind B1 · utility

Assignees

• NANJING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS · CN
• NANTONG INSTITUTE OF NANJING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS CO., LTD. · CN

Inventors

• Zhikuang Cai · 安丰镇, CN
• Guopeng Zhou · Shanghai, CN
• Haijun Shen · 安丰镇, CN
• Binbin Xu · Xi'an, CN
• Jiafei Yao · 安丰镇, CN
• Henglu Wang · 安丰镇, CN
• Zushuai Xie · 安丰镇, CN
• Jian Xiao · Chengdu, CN
• Zixuan Wang · 安丰镇, CN
• Yufeng Guo · 安丰镇, CN

Key dates

• Filing date: Jan 10, 2023
• Grant date: Jan 7, 2025
• Expiry date: Jan 10, 2043

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318563
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A circuit for post-binding testing of a 2.5D chiplet includes an interposer-dedicated TAP controller, an interposer test interface circuit and a chiplet test output control circuit. A chiplet test configuration register and its corresponding instructions are newly added for the interposer-dedicated TAP controller. The interposer test interface circuit uses an output control signal of the chiplet test configuration register to select the opening or closing of a test signal channel between an interposer and a chiplet. The chiplet test output control circuit uses the chiplet test configuration register to output a control signal for control of a test data output of the chiplet on the interposer.