Variable reference clock signal for data transmission between PHY layer and MAC layer
US12189549B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2023 |
| Grant date | Jan 7, 2025 |
| Priority date | — |
| Expiry date | Mar 27, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for data transmission includes a physical (PHY) layer which has a rate detection module which determines an adopted clock rate. The rate detection module provides a rate detection signal indicative of the adopted clock rate. The PHY layer includes a reference clock generator which has an input coupled to receive the rate detection signal and an output to provide a reference clock output. The PHY layer includes a PHY interface which has a first input coupled to receive the reference clock output, a data input and a data output. The PHY interface receives data from a MAC interface at the data input and transmits data to the MAC interface through the data output responsive to the reference clock output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.