Low latency nodes fusion in a reconfigurable data processor
US12189570B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 2023 |
| Grant date | Jan 7, 2025 |
| Priority date | — |
| Expiry date | Jun 26, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/433
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system includes an array of reconfigurable units and a compiler configured to generate a pipeline of n computational nodes related to a dataflow graph, interleaved between n+1 buffers on the array of reconfigurable units. Each computational node is coupled to perform calculations based on data received from an immediately preceding buffer of the n+1 buffers and store results of the calculations into an immediately following buffer of the n+1 buffers after a latency. The compiler is further configured to remove a buffer of the n+1 buffers from the pipeline based on a comparison of the latencies of the computational nodes. A corresponding method is also disclosed herein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.