Dynamic memory management apparatus and method for HLS
US12189950B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 22, 2022 |
| Grant date | Jan 7, 2025 |
| Priority date | — |
| Expiry date | Feb 16, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F16/90335
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a dynamic memory management apparatus and method for HLS, the apparatus has several searching and caching modules and several modifying and writing-back modules, the searching and caching modules are in connection with a DRAM storing module and a BRAM buffer, respectively, and the modifying and writing-back modules are in connection with the DRAM storing module and the BRAM buffer, respectively, the BRAM buffer is for caching information about nodes on a search path and registering information about modification made to the nodes. To remedy the defect that the traditional operating system is directly transplanted to the FPGA and has low execution efficiency, the present invention utilizes the advantage of the large capacity of the DRAM on the FPGA to realize efficient dynamic memory allocation and deallocation, and improve the usability and code reusability of HLS.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.