Computer system, memory device formed on a wafer on wafer stack in the computer system and memory control method applied to the computer system based on wafer-on-wafer architecture
US12189954B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 5, 2022 |
| Grant date | Jan 7, 2025 |
| Priority date | — |
| Expiry date | Jan 27, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system based on wafer-on-wafer architecture is provided, comprising a memory device and a logic circuit layer stacked in a wafer on wafer structural configuration. The memory device comprises a memory array and a circuit driver. The memory array comprises a shared circuit path and a plurality of memory cells, wherein the shared circuit path is connected to the memory cells. The circuit driver is connected to the shared circuit path, driving the memory cells. The logic circuit layer comprises a plurality of bonding pads for signal transmission, and a latency controller, connected to the memory array through the bonding pads, adjusting the number of memory cells connecting the shared circuit path, thereby dynamically adjusting the latency characteristics of the memory array. Embodiments of the memory device and the memory control method are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.