Processing elements array that includes delay queues between processing elements to hold shared data
US12190224B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2020 |
| Grant date | Jan 7, 2025 |
| Priority date | — |
| Expiry date | Nov 9, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/5027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing element architecture adapted to a convolution comprises a plurality of processing elements and a delayed queue circuit. The plurality of processing elements includes a first processing element and a second processing element, wherein the first processing element and the second processing element perform the convolution according to a shared datum at least. The delayed queue circuit connects to the first processing element and connects to the second processing element. The delayed queue circuit receives the shared datum sent by the first processing element, and sends the shared datum to the second processing element after receiving the shared datum and waiting for a time interval.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.