Arithmetic unit for deep learning acceleration
US12190243B2 · kind B2 · utility
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17Claims
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Key dates
| Filing date | Jan 19, 2023 |
| Grant date | Jan 7, 2025 |
| Priority date | — |
| Expiry date | Jan 19, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N20/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a reconfigurable stream switch and an arithmetic circuit. The stream switch, in operation, streams data. The arithmetic circuit has a plurality of inputs coupled to the reconfigurable stream switch. In operation, the arithmetic circuit generates an output according to AX+BY+C, where A, B and C are vector or scalar constants, and X and Y are data streams streamed to the arithmetic circuit through the reconfigurable stream switch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.