Gate driving circuit and display apparatus including the same
US12190791B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 2023 |
| Grant date | Jan 7, 2025 |
| Priority date | — |
| Expiry date | May 3, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Provided is a gate driving circuit comprising an N-th stage and an N+1-th stage. The N-th stage outputs an N-th scan gate signal based on an N-th scan clock signal, a voltage of a QN node, and a voltage of a QBN node and to output an N-th carry signal based on an N-th carry clock signal, the voltage of the QN node, and the voltage of the QBN node. The N+1-th stage outputs an N+1-th scan gate signal based on an N+1-th scan clock signal, a voltage of a QN+1 node, and the voltage of the QBN node and an N+1-th carry signal based on an N+1-th carry clock signal, the voltage of the QN+1 node, and the voltage of the QBN node. The N-th stage and the N+1-th stage share an inverting circuit. The inverting circuit controls the QBN node based on a third signal. N is a positive integer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.