Memory device and program method of ground select transistors
US12190954B2 · kind B2 · utility
0Cited by
13References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2022 |
| Grant date | Jan 7, 2025 |
| Priority date | — |
| Expiry date | Jan 17, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3459
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A program method includes applying a first voltage to a plurality of bit lines, applying a second voltage to a common source line (CSL), and performing a program loop by applying a program voltage and a verify voltage to each of a plurality of ground selection lines (GSLs) positioned between one bit line among the plurality of bit lines and the CSL. The program loop is performed on both a program completed cell in which a program is completed by applying the program voltage and a program target cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.