Integrated circuit packages having stress-relieving features
US12191268B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 2024 |
| Grant date | Jan 7, 2025 |
| Priority date | — |
| Expiry date | Jul 19, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/16227
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Expansion compensating structures are formed in redistribution layers of a wafer-level chip-scale integrated circuit package (WLCSP) or other IC package having a low-expansion substrate. The structures include micromechanical actuators designed and oriented to move solder bumps attached to them in the same direction and distance as a function of temperature as do pads to which they may be connected on a higher-expansion substrate such as a printed circuit board. Expansion compensated IC packages incorporating these expansion compensating structures are provided, as well as expansion compensated assemblies containing one or more of these IC packages. Methods of fabricating expansion compensated IC packages requiring minimal changes to existing commercial WLCSP fabrication processes are also provided. These devices and methods result in assemblies having improved board-level reliability during thermal cycling, and allow the use of larger IC die sizes in WLCSP technology.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.