One-dimensional hard-input FEC receiver for digital communication
US12191995B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Jul 8, 2022 |
| Grant date | Jan 7, 2025 |
| Priority date | — |
| Expiry date | Nov 19, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0061
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital receiver based on one-dimensional hard demapping of an input symbol stream (FEC encoded) is configured to utilize LLRs created to have bit-specific magnitude values to improve the probability that the included decoder (such as an LDPC decoder) properly recovers each bit from the original stream. The digital receiver may be used with various types of data modulation schemes (e.g., PAM3, PAM4, DSQ8, etc.), with a specific set of LLR magnitudes created for each modulation scheme.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.