Allocation of shared reserve memory
US12192122B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2024 |
| Grant date | Jan 7, 2025 |
| Priority date | — |
| Expiry date | Feb 20, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/9047
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A device includes ports, a packet processor, and a memory management circuit. The ports communicate packets over a network. The packet processor processes the packets using queues. The memory management circuit maintains a shared buffer in a memory and adaptively allocates memory resources from the shared buffer to the queues, maintains in the memory, in addition to the shared buffer, a shared-reserve memory pool for use by the queues, identifies, among the queues, a queue that requires additional memory resources, the queue having an occupancy that is (i) above a current value of a dynamic threshold, rendering the queue ineligible for additional allocation from the shared buffer, and (ii) no more than a defined margin above the current value of the dynamic threshold, rendering the queue eligible for allocation from the shared-reserve memory pool, and allocates memory resources to the identified queue from the shared-reserve memory pool.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.