Monitoring circuit of phase locked loop and operating method thereof
US12192315B2 · kind B2 · utility
0Cited by
6References
20Claims
0Family size
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Key dates
| Filing date | Sep 13, 2022 |
| Grant date | Jan 7, 2025 |
| Priority date | — |
| Expiry date | Sep 13, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2824
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A monitoring circuit for a high frequency signal includes: a phase locked loop configured to generate a divided output signal with respect to an input signal based on a plurality of dividers; a plurality of dividing monitoring circuits configured to receive dividing input signals and dividing output signals respectively corresponding to the plurality of dividers, and output dividing error signals; and a jitter monitoring circuit configured to output a jitter error signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.