System for scan mode exit and methods for scan mode exit
US12196804B2 · kind B2 · utility
0Cited by
6References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2022 |
| Grant date | Jan 14, 2025 |
| Priority date | — |
| Expiry date | Mar 21, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/333
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Resetting an integrated circuit (IC) by reset circuit of the IC comprises receiving a clock signal and a data signal. A sequence of bits of the data signal is stored in a memory based on the clock signal. A test mode signal is received and the sequence of bits is decoded in response to receiving the test mode signal. One of adjusting a counter value of a counter of the reset circuitry and outputting a reset signal corresponding to the counter value is performed based on the decoded sequence of bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.