Dynamic power allocation for memory using multiple interleaving patterns
US12197266B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 22, 2022 |
| Grant date | Jan 14, 2025 |
| Priority date | — |
| Expiry date | Dec 16, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are disclosed for dynamic power allocation for memory using multiple interleaving patterns. For example, a system may include a set of memory devices, including a first subset and a second subset, and a memory management circuitry configured to translate virtual addresses into physical addresses of memory locations in the set of memory devices using a first interleaving pattern when operating in a first mode; and translate virtual addresses using a second interleaving pattern when operating in a second mode. The first and second interleaving patterns both map virtual addresses in a first range exclusively to memory devices in the first subset. The first interleaving pattern maps virtual addresses in a second range to memory devices in the first subset and in the second subset. The second interleaving pattern maps virtual addresses in the second range exclusively to memory devices in the first subset.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.