PCIE DPC SMI storm prevention system
US12197280B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2023 |
| Grant date | Jan 14, 2025 |
| Priority date | — |
| Expiry date | Jul 4, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3075
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Peripheral Component Interconnect express (PCIe) Downstream Port Containment (DPC) System Management Interrupt (SMI) storm prevention system includes a Basic Input/Output System (BIOS) subsystem coupled to a first PCIe device. In response to an error being experienced in the first PCIe device and causing the first PCIe device to perform DPC operations, the BIOS subsystem receives a plurality of SMIs that are each configured to begin a System Management Mode (SMM). The BIOS subsystem tracks a number of the plurality of SMIs in a BIOS database and determines when the number of the plurality of SMIs has reached a DPC SMI storm threshold. In response to the number of the plurality of SMIs reaching the DPC SMI storm threshold, the BIOS subsystem prevents use of a link to the first PCIe device and prevents an operating system from performing recovery operations to recover the first PCIe device from the error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.