Double-mapping technique of I/O latency optimization
US12197728B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2023 |
| Grant date | Jan 14, 2025 |
| Priority date | — |
| Expiry date | Jul 12, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In at least one embodiment, processing can include: receiving, at a first node, a read operation that reads content of a logical address, wherein a second node, but not the first node, owns the logical address; and performing optimized read processing for the read operation. The optimized read processing can include: performing, in parallel, first processing that obtains a first address hint and first content corresponding to the logical address, and second processing that obtains a second address hint corresponding to the logical address; determining whether the first and second address hints match; if the first and second address hints match, determining that first content is valid content stored at the target logical address; if the first and second address hints do not match, determining the first content is not stored at the logical address, and using the second address hint to obtain second content stored at the logical address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.