Multiplier and adder in systolic array
US12197890B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 16, 2021 |
| Grant date | Jan 14, 2025 |
| Priority date | — |
| Expiry date | Sep 10, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8046
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The subject matter described herein provides systems and techniques for the design and use of multiply-and-accumulate (MAC) units to perform matrix multiplication by systolic arrays, such as those used in accelerators for deep neural networks (DNNs). These MAC units may take advantage of the particular way in which matrix multiplication is performed within a systolic array. For example, when a matrix A is multiplied with a matrix B, the scalar value, a, of the matrix A is reused many times, the scalar value, b, of the matrix B may be streamed into the systolic array and forwarded to a series of MAC units in the systolic array, and only the final values and not the intermediate values of the dot products, computed for the matrix multiplication, may be correct. MAC unit hardware that is particularized to take advantage of these observations is described herein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.