Preemption in a machine learning hardware accelerator
US12197959B2 · kind B2 · utility
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20Claims
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Assignee
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Key dates
| Filing date | Dec 21, 2020 |
| Grant date | Jan 14, 2025 |
| Priority date | — |
| Expiry date | Jan 5, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4881
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure describes a system and method for preempting a long-running process with a higher priority process in a machine learning system, such as a hardware accelerator. The machine learning hardware accelerator can be a multi-chip system including semiconductor chips that can be application-specific integrated circuits (ASIC) designed to perform machine learning operations. An ASIC is an integrated circuit (IC) that is customized for a particular use.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.